Vertically stacked SiGe nanowire array channel CMOS transistors

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around n- and p-FETs, fabricated using these stacked NW arrays as the channel (L-g >= 0.35 mu m), exhibit excellent device performance with high I-ON /I-OFF ratio (similar to 10(6)), near ideal subthreshold slope (similar to 62-75 mV/dec) and low drain induced barrier-lowering (similar to 20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate.