Accurate delay models of CMOS CML circuits for design optimization

This paper presents accurate delay models of current-mode logic (CML) circuits for equation-based circuit optimization. We propose accurate edge-rate-dependent delay models of a CML buffer, a latch, and a multiplexer. Newly proposed delay models have compatibility with geometric programming and scalability for the hierarchical design of CML-based circuits, thereby enabling true constraint-driven equation-based design optimization. In order to validate these models, we show the modeling errors of unit CML gates over a wide range of delay and edge rates. N-stage CML buffers and a 28 Gb/s serializer in 45 nm CMOS technology are optimized for minimum power dissipation. The numerical experiments indicates that the proposed delay models can guarantee the intended operation of CML-based circuits when used in the equation-based design optimization.