Design and implementation of 2bit Vedic multiplier at 16nm using PTL logic

被引：0

作者：

Sharma, Kshitij ^{[1
]}

Garg, Anubhav ^{[1
]}

Agrawal, Deepak ^{[1
]}

Mehra, Anu ^{[1
]}

Singhal, Smita ^{[1
]}

机构：

[1] Amity Univ, ASET, Dept ECE, Noida, Uttar Pradesh, India

来源：

2018 FOURTH INTERNATIONAL CONFERENCE ON COMPUTING COMMUNICATION CONTROL AND AUTOMATION (ICCUBEA) | 2018年

关键词：

Vedic multiplier; CMOS(Complementary Metal Oxide Semiconductor); PTL(Pass Transistor Logic);

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

As the demand for high speed computations have increased, Vedic multipliers have been implemented in circuits. In this paper, a 2bit Vedic multiplier has been implemented using Pass Transistor Logic. The implementation of 2 bit Vedic Multiplier using PTL results in 59.63% power reduction and 42.07% reduction in delay as compared to CMOS design at typical value of 0.9V. The tool for implementation is ngspice. The implementation technology of the circuit is 16 nm.

引用

页数：5

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