Design and Analysis of a CMOS 180-nm Fractional-N Frequency Synthesizer

被引：0

作者：

Parvathy, P. ^{[1
]}

Saraswathi, N. ^{[1
]}

机构：

[1] SRM Univ, Dept Elect & Commun Engn, Kattakulathur 603203, Tamil Nadu, India

来源：

NANOELECTRONIC MATERIALS AND DEVICES, VOL III | 2018年 / 466卷

关键词：

D O I：

10.1007/978-981-10-7191-1_5

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design of a Fractional-N Frequency Synthesizer in CMOS 180-nm that operates in GHz range is discussed. The proposed frequency synthesizer is realized using a phase-locked loop with phase frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), and a programmable frequency divider. The characteristics of the PFD are extremely linear as one of the input frequencies is modulated. The frequency divider deigned is a programmable one as it can generate noninteger division ratios unlike an integer PLL.

引用

页码：37 / 49

页数：13

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