A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO

被引：58
|
作者：
Heng, CH
Song, BS
机构：
[1] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA
[2] Univ Calif San Diego, Dept Elect & Comp Engn, La Jolla, CA 92093 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2003年 / 38卷 / 06期
关键词：
frequency synthesizers; phase-locked loops; phase noise; Delta Sigma modulation;
D O I：
10.1109/JSSC.2003.811872
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 1.8-GHZ fractional-N frequency synthesizer implemented in 0.6-mum CMOS with an on-chip multiphase voltage-contiolled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture-randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20-kHz loop bandwidth and -118 dBc/Hz at 1-MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step,smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 min x 2.9 min.
引用
收藏
页码：848 / 854
页数：7
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