Reliability evaluation of chip scale packages by FEA and microDAC

The thermo-mechanical reliability of chip scale packages (CSP) is determined by the package technology as the package has to compensate the thermal mismatch between the silicon die and the substrate. In contrast to flip chip technology the CSP is usually assembled on the printed circuit board without underfilling. Nonlinear Finite Element Analysis has been performed to compare different CSP approaches under thermal cyclic load and to allow a life time estimation with respect to the various geometric design parameters and to the complex mechanical behavior of the materials used. Numerical simulation has been used to support CSP development and to classify different types of CSP according to their reliability.