Fully working 1.10μm2 embedded 6T-SRAM technology with high-k gate dielectric device for ultra low power applications

被引：0

作者：

Ryu, HJ ^{[1
]}

Chung, WY ^{[1
]}

Jang, YJ ^{[1
]}

Lee, YJ ^{[1
]}

Jung, HS ^{[1
]}

Oh, CB ^{[1
]}

Kang, HS ^{[1
]}

Kim, YW ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Syst LSI Div, Semicond Business, Yongin 449711, South Korea

来源：

2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Ultra low power 1.10 mum(2) 6T-SRAM chip with HfO2-A1(2)O(3) gate dielectric was for the first time successfully demonstrated for the system-on-chip applications. By carefully optimizing gate pre-doping process, gate leakage current was dramatically suppressed and poly deletion was reduced. Device performance was improved by 15% and 12% for NFET and PFET, respectively. The threshold voltage of long channel transistor was well controlled to the acceptable value (0.4V) by channel engineering. Equivalent oxide thickness of HfO2-Al2O3 film was 17 Angstrom and gate leakage current density was 1000 times lower than that of the oxyrritride. Current performance of 90nm gate length NFET and PFET with HfO2-Al2O3 were 335 and 115 muA/pm, while Ioff were 0.9 and 2.OpA/mum, respectively. SNM value of 1.10mum(2) 6T-SRAM bit cell was 340mV at Vdd=1.2V. Stand-by current of the SRAM chips with Hf02-A1203 was decreased by 2 orders, while access time was 1.65 times larger compared with that of SRAM chips with oxynitride at Vdd=1.2V. Introduction

引用

页码：38 / 39

页数：2

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