Nanoscale Tri Gate MOSFET for Ultra Low Power Applications Using High-k Dielectrics

The Triple-Gate (TG) MOSFET has emerged as one of the promising devices to extend CMOS technology beyond the scaling limit of conventional CMOS technology. Triple gate MOSFET has an excellent scalability and better Short Channel Effect immunity. They are used for CMOS applications beyond the 22 nm node. In order to reduce the leakage current for device beyond the 22 nm, the gate dielectric is replaced with different High-k dielectric material. Triple Gate MOSFET is developed using Sentaurus simulator and its performance is analyzed for various device parameters. It is observed that the integation of high-k gate oxide dielectric material in Triple gate MOSFET significantly reduce the short channel effects and the leakage current. The parameters such as ON current, OFF current, Ion/Ioff ratio, DIBL(Drain Induced Barrier Lowering), transconductance, transconductance generation factor, output resistance, intrinsic gain and intrinsic gate capacitances are analyzed in this paper. The suitability of nanoscale Triple gate MOSFET for circuit applications is observed with the help of an inverter circuit and their gain values are calculated for VLSI low power applications.