A test algorithm for multiple-valued logic combinational circuits

被引：0
|
作者：
Levashenko, V [1 ]
Moraga, K
Kholovinski, G
Yanushkevich, S
Shmerko, V
机构：
[1] Inst Econ, Minsk, BELARUS
[2] Univ Dortmund, Dortmund, Germany
[3] Inst Technol, Szczecin, Poland
[4] Inst Informat & Radion Engn, Minsk, BELARUS
来源：
AUTOMATION AND REMOTE CONTROL | 2000年 / 61卷 / 05期
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The new test algorithm designed for multiple-valued logic combinational circuits is a generalization of the D-algorithm and detects single faults in circuit production technologies. D-cubes of multiple-valued logic circuits are formed by computing the directional logical derivatives of the functions they implement. The algorithm is invariant to the type of the multiple-valued logic gates or the class of detected errors in a circuit. A classification of the faults in such circuits is given and the results of an experiment are presented.
引用
收藏
页码：844 / 857
页数：14
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