CLOCKED SEMI-FLOATING-GATE ULTRA LOW-VOLTAGE INVERTING CURRENT MIRROR

被引：0
|
作者：
Berg, Y. [1 ]
Mirmotahari, O. [1 ]
机构：
[1] Univ Oslo, Dept Informat, N-0316 Oslo, Norway
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2009年
关键词：
CIRCUITS;
D O I：
10.1109/SOCCON.2009.5398036
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper we present a low voltage inverting current mirror based on clocked semi-floating-gate transistors used in low-voltage digital CMOS circuits [1]. By applying offsets to semifloating-gate nodes the current level may be increased compared to non-floating-gate design applying ultra low supply voltages. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. The proposed inverted current mirror can operate at supply voltages below 2507mV. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90nm, CMOS process.
引用
收藏
页码：307 / 310
页数：4
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