On-Chip Supervised Learning Rule for Ultra High Density Neural Crossbar using Memristor for Synapse and Neuron

The memristor-based neural learning network is considered as one of the candidates for future computing systems thanks to its low power, high density and defect-tolerance. However, its application is still hindered by the limitations of huge neuron structure and complicated learning cell. In this paper, we present a memristor-based neural crossbar circuit to implement on-chip supervised learning rule. In our work, activation function of neuron is implemented with simple CMOS inverter to save area overhead. Importantly, we propose a compact learning cell with a crossbar latch consisting of two anti-parallel oriented binary memristors. This scheme allows high density integration and could improve the reliability of learning circuit. We describe firstly the circuit architecture, memristor model and operation process of supervised learning rule. Afterwards we perform transient simulation with CMOS 40nm design kit to validate the function of proposed learning circuit. Analysis and evaluation demonstrate that our circuit show great potential in on-chip learning.