Ultra low-power CMOS IC using partially-depleted SOI technology

被引：2
|
作者：
Ebina, A [1 ]
Kadowaki, T [1 ]
Sato, Y [1 ]
Yamaguchi, M [1 ]
机构：
[1] SEIKO EPSON CORP, Semicond Operat Div, IC R&D Dept, Fujimi, Nagano, Japan
来源：
PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2000年
关键词：
D O I：
10.1109/CICC.2000.852617
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We developed the ultra low power IC for a wrist-watch application. The realized operation current and voltage were 30nA and 0.42V respectively. This extreme low power operation was achieved by taking full advantage of body-floated devices with the partially-depleted SOI CMOS technology.
引用
收藏
页码：57 / 60
页数：4
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