Reference model based RTL verification: An integrated approach

被引：6

作者：

Hung, WNN ^{[1
]}

Narasimhan, N ^{[1
]}

机构：

[1] Synplic Inc, Sunnyvale, CA 94086 USA

来源：

NINTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/HLDVT.2004.1431221

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present an approach that makes reference model based formal verification both complete and practical in an industrial setting. This paper describes a novel approach to conduct this exercise, by seamlessly integrating formal equivalence verification (FEV) techniques within a verification flow suited to formal property verification (FPV). This enables us to take full advantage of the rich expressive power of temporal specification languages and help guide the FEV tools so as to enable reference model verification to an extent that was never attempted before. We have successfully applied our approach to challenging verification problems at Intel(R).

引用

页码：9 / 13

页数：5

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