Reference model based RTL verification: An integrated approach

被引：6

作者：

Hung, WNN ^{[1
]}

Narasimhan, N ^{[1
]}

机构：

[1] Synplic Inc, Sunnyvale, CA 94086 USA

来源：

NINTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/HLDVT.2004.1431221

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present an approach that makes reference model based formal verification both complete and practical in an industrial setting. This paper describes a novel approach to conduct this exercise, by seamlessly integrating formal equivalence verification (FEV) techniques within a verification flow suited to formal property verification (FPV). This enables us to take full advantage of the rich expressive power of temporal specification languages and help guide the FEV tools so as to enable reference model verification to an extent that was never attempted before. We have successfully applied our approach to challenging verification problems at Intel(R).

引用

页码：9 / 13

页数：5

共 50 条

[1] Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL
Jain, Abhishek
Gupta, Hima
Jana, Sandeep
Kumar, Krishna
INTERNATIONAL JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS, 2014, 5 (02) : 77 - 82
[2] CVC: THE C TO RTL COMPILER FOR CALLBACK-BASED VERIFICATION MODEL
Ito, Yasuhiro
Sugawara, Yutaka
Inaba, Mary
Hiraki, Kei
2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2, 2008, : 498 - +
[3] Automatic memory reductions for RTL model verification
Manolios, Panagiotis
Srinivasan, Sudarshan K.
Vroon, Daron
IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, ICCAD, 2006, : 40 - +
[4] AUTOMATED RTL VERIFICATION BASED ON PREDICATE CALCULUS
LANGEVIN, M
LECTURE NOTES IN COMPUTER SCIENCE, 1991, 531 : 116 - 125
[5] Towards an Integrated Approach to Verification and Model-Based Testing in System Engineering
Lefticaru, Raluca
Konur, Savas
Yildirim, Unal
Uddin, Amad
Campean, Felician
Gheorghe, Marian
2017 IEEE INTERNATIONAL CONFERENCE ON INTERNET OF THINGS (ITHINGS) AND IEEE GREEN COMPUTING AND COMMUNICATIONS (GREENCOM) AND IEEE CYBER, PHYSICAL AND SOCIAL COMPUTING (CPSCOM) AND IEEE SMART DATA (SMARTDATA), 2017, : 131 - 138
[6] A novel formal verification approach for RTL hardware IP cores
Djemal, R
Dhouib, MA
Dellacherie, S
Tourki, R
COMPUTER STANDARDS & INTERFACES, 2005, 27 (06) : 637 - 651
[7] A game theory approach for RTL security verification resources allocation
Wang, Haoyi
Cai, Yici
Zhou, Qiang
CCF TRANSACTIONS ON HIGH PERFORMANCE COMPUTING, 2021, 3 (01) : 57 - 69
[8] A game theory approach for RTL security verification resources allocation
Haoyi Wang
Yici Cai
Qiang Zhou
CCF Transactions on High Performance Computing, 2021, 3 : 57 - 69
[9] Accelerated verification of RTL assertions based on satisfiability solvers
Fraer, R
Ikram, S
Kamhi, G
Leonard, T
Mokkedem, A
SEVENTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS, 2002, : 107 - 110
[10] A distance-based approach to modelling reference signature for verification
Mlaba, A. S. P.
Gwetu, M. V.
Viriri, S.
2017 CONFERENCE ON INFORMATION COMMUNICATION TECHNOLOGY AND SOCIETY (ICTAS), 2017,

← 1 2 3 4 5 →