Loop filter design considerations for clock and data recovery circuits

被引：0

作者：

Ou, J ^{[1
]}

Caggiano, MF ^{[1
]}

机构：

[1] Rutgers State Univ, Dept Elect & Comp Engn, Coll Engn, Piscataway, NJ 08854 USA

来源：

2003 SOUTHWEST SYMPOSIUM ON MIXED-SIGNAL DESIGN | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a detailed 3(rd) order analysis that accounts for charge pump output resistance, bandwidth controlling resistor, damping capacitor and ripple capacitor as well as other important PLL parameters such as K-d, the phase detector gain and K-vco, the VCO gain. Equations derived in this paper can be implemented in commercial software programs such as MATLAB to generate behavior models.

引用

页码：81 / 86

页数：6

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