Novel current mode CMOS multiple-valued logic neuron

被引：0

作者：

Teng, Daniel H. Y. ^{[1
]}

机构：

[1] Univ Saskatchewan, Dept Elect & Comp Engn, Saskatoon, SK, Canada

来源：

2006 Canadian Conference on Electrical and Computer Engineering, Vols 1-5 | 2006年

关键词：

Multiple-Valued Logic (MVL); current-mode CMOS; logic (CMCL); neural network;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper proposes a new neuron model that has multiple-valued logic inputs, weights, and outputs. The new model results in improved speed due to its carry free operations. The interconnection complexity of neural network based on this model can also be reduced significantly due to the inherent properties from the multiple-valued logic. Dependent the layers of neural networks, at least 50 percentage of reduction in the interconnection area can be achieved with 4-valued logic neurons. Circuit implementation of the model using current-mode CMOS design technique is also discussed with SPICE simulations.

引用

页码：1911 / 1914

页数：4

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