Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field

被引：13

作者：

Kim, Sangwan ^{[1
]}

Choi, Woo Young ^{[2
]}

机构：

[1] Ajou Univ, Dept Elect & Comp Engn, Suwon 16499, South Korea

[2] Sogang Univ, Dept Elect Engn, Seoul 04107, South Korea

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2017年 / 56卷 / 08期

基金：

新加坡国家研究基金会;

关键词：

CAPACITANCE;

D O I：

10.7567/JJAP.56.084301

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

In this work, the accuracy of a compact current-voltage (I-V) model for double-gate n-channel tunnel field-effect transistors (TFETs) is improve by considering outer and inner gate fringing field effects. The refined model is benchmarked against technology computer-aided design (TCAD) device simulations and compared against a previously published compact model. The normalized root-mean-square error for current in the linear region of operation (i.e., for 0.05V drain voltage) is reduced from similar to 593 to similar to 5%. (C) 2017 The Japan Society of Applied Physics

引用

页数：5

共 50 条

[1] Compact Current Model of Single-Gate/Double-Gate Tunneling Field-Effect Transistors
Yu, Yun Seop
Najam, Faraz
[J]. JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY, 2017, 12 (05) : 2014 - 2020
[2] BREAKDOWN PHENOMENA IN DOUBLE-GATE FIELD-EFFECT TRANSISTORS
COBBOLD, RSC
TROFIMENKO, FN
[J]. PROCEEDINGS OF THE IEEE, 1964, 52 (11) : 1375 - &
[3] Thin-body effects in double-gate tunnel field-effect transistors
Chien, Nguyen Dang
Thai, Bui Huu
Shih, Chun-Hsing
[J]. JOURNAL OF PHYSICS D-APPLIED PHYSICS, 2024, 57 (21)
[4] Stochastic Variability in Silicon Double-Gate Lateral Tunnel Field-Effect Transistors
Leung, Greg
Chui, Chi On
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (01) : 84 - 91
[5] Scaling Length Theory of Double-Gate Interband Tunnel Field-Effect Transistors
Liu, Lu
Mohata, Dheeraj
Datta, Suman
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (04) : 902 - 908
[6] Analytical Drain Current Modeling of Double-Gate Tunnel Field-Effect Transistors
Pal, Arnab
Dutta, Aloke K.
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (08) : 3213 - 3221
[7] Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors
Choi, Woo Young
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS, 2017, 56 (04)
[8] Explicit drain current model of junctionless double-gate field-effect transistors
Yesayan, Ashkhen
Pregaldiny, Fabien
Sallese, Jean-Michel
[J]. SOLID-STATE ELECTRONICS, 2013, 89 : 134 - 138
[9] Compact Potential Model for Si1-xGex/Si Heterojunction Double-Gate Tunnel Field-Effect Transistors (TFETs)
Kim, Sangwan
Choi, Woo Young
[J]. JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2018, 18 (09) : 5953 - 5958
[10] A Quasi-Analytical Model for Double-Gate Tunneling Field-Effect Transistors
Pan, Andrew
Chui, Chi On
[J]. IEEE ELECTRON DEVICE LETTERS, 2012, 33 (10) : 1468 - 1470

← 1 2 3 4 5 →