A Configurable Length, Fused Multiply-Add Floating Point Unit for a VLIW Processor

被引：2
|
作者：
Chouliaras, V. A. [1 ]
Manolopoulos, K. [2 ]
Reisis, D. [2 ]
机构：
[1] Univ Loughborough, Dept Elect & Elect Engn, Loughborough, Leics, England
[2] Natl & Kapodistrian Univ Athens, Elect Lab, Dept Phys, Athens, Greece
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2009年
关键词：
D O I：
10.1109/SOCCON.2009.5398088
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The efficiency of Fused Multiply Add units plays a key role in the processor's performance for a variety of applications. A design keeping the advantages of the FMA regarding the latency and the hardware utilization and also improving the result's accuracy in both normalized and denormalized numbers is the subject of this work. The FMA unit has configurable latency and it is integrated in a VLIW processor. The VLSI TSMC 0.13 implementation achieved an operating frequency of 232.6 MHz and a final post-routed area of 121900.478 um(2).
引用
收藏
页码：93 / +
页数：2
相关论文
共 50 条
  • [1] Floating-point fused multiply-add architectures
    Quinnell, Eric
    Swartzlander, Earl E., Jr.
    Lemonds, Carl
    CONFERENCE RECORD OF THE FORTY-FIRST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1-5, 2007, : 331 - +
  • [2] An efficient multiple precision floating-point Multiply-Add Fused unit
    Manolopoulos, K.
    Reisis, D.
    Chouliaras, V. A.
    MICROELECTRONICS JOURNAL, 2016, 49 : 10 - 18
  • [3] Improved Fused Floating Point Add-Subtract and Multiply-Add Unit for FFT Implementation
    Palsodkar, Prasanna
    Gurjar, Ajay
    2014 2ND INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS), 2014,
  • [4] Fused Multiply-Add for Variable Precision Floating-Point
    Nannarelli, Alberto
    32ND IEEE INTERNATIONAL SYSTEM ON CHIP CONFERENCE (IEEE SOCC 2019), 2019, : 342 - 347
  • [5] Floating-point fused multiply-add with reduced latency
    Lang, T
    Bruguera, JD
    ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 2002, : 145 - 150
  • [6] Proxy Bits for Low Cost Floating-Point Fused Multiply-Add Unit
    Kim, Hyunpil
    Moon, Sangook
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2016, 25 (10)
  • [7] Bridge Floating-Point Fused Multiply-Add Design
    Quinnell, Eric
    Swartzlander, Earl E., Jr.
    Lemonds, Carl
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (12) : 1726 - 1730
  • [8] Development of a RISC-V-conform fused multiply-add floating-point unit
    Kaiser F.
    Kosnac S.
    Brüning U.
    Supercomputing Frontiers and Innovations, 2019, 6 (02) : 64 - 74
  • [9] Implementation of Low Power and Area Efficient Floating-Point Fused Multiply-Add Unit
    Dhanabal, R.
    Sahoo, Sarat Kumar
    Bharathi, V.
    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON SOFT COMPUTING SYSTEMS, ICSCS 2015, VOL 1, 2016, 397 : 329 - 342
  • [10] Floating-Point Fused Multiply-Add under HUB Format
    Hormigo, Javier
    Villalba-Moreno, Julio
    Gonzalez-Navarro, Sonia
    2020 IEEE 27TH SYMPOSIUM ON COMPUTER ARITHMETIC (ARITH), 2020, : 1 - 8
12345