A Configurable Length, Fused Multiply-Add Floating Point Unit for a VLIW Processor

被引：2

作者：

Chouliaras, V. A. ^{[1
]}

Manolopoulos, K. ^{[2
]}

Reisis, D. ^{[2
]}

机构：

[1] Univ Loughborough, Dept Elect & Elect Engn, Loughborough, Leics, England

[2] Natl & Kapodistrian Univ Athens, Elect Lab, Dept Phys, Athens, Greece

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2009年

关键词：

D O I：

10.1109/SOCCON.2009.5398088

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The efficiency of Fused Multiply Add units plays a key role in the processor's performance for a variety of applications. A design keeping the advantages of the FMA regarding the latency and the hardware utilization and also improving the result's accuracy in both normalized and denormalized numbers is the subject of this work. The FMA unit has configurable latency and it is integrated in a VLIW processor. The VLSI TSMC 0.13 implementation achieved an operating frequency of 232.6 MHz and a final post-routed area of 121900.478 um(2).

引用

页码：93 / +

页数：2

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