An efficient multiple precision floating-point Multiply-Add Fused unit

被引：11
|
作者：
Manolopoulos, K. [1 ]
Reisis, D. [1 ]
Chouliaras, V. A. [2 ]
机构：
[1] Natl Kapodistrian Univ Athens, Dept Phys, Elect Lab, Phys Bldg 4 & 5, Athens 15784, Greece
[2] Univ Loughborough, Dept Elect & Elect Engn, Loughborough, Leics, England
来源：
MICROELECTRONICS JOURNAL | 2016年 / 49卷
关键词：
Floating-point; Multiply-Add Fused; Multiple precision; VLSI; ARCHITECTURES; ALGORITHMS; DESIGN;
D O I：
10.1016/j.mejo.2015.10.012
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Multiply-Add Fused (MAF) units play a key role in the processor's performance for a variety of applications. The objective of this paper is to present a multi-functional, multiple precision floating-point Multiply-Add Fused (MAF) unit. The proposed MAF is reconfigurable and able to execute a quadruple precision MAF instruction, or two double precision instructions, or four single precision instructions in parallel. The MAF architecture features a dual-path organization reducing the latency of the floating-point add (FADD) instruction and utilizes the minimum number of operating components to keep the area low. The proposed MAF design was implemented on a 65 nm silicon process achieving a maximum operating frequency of 293.5 MHz at 381 mW power. (C) 2015 Elsevier Ltd. All rights reserved.
引用
收藏
页码：10 / 18
页数：9
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