Pseudo Multi-Port SRAM Circuit for Image Processing in Display Drivers

NxN filter operations are frequently used in various image processing algorithms in display driver circuits. The implementation of the NxN filter requires a storage element to temporarily retain N or N-1 lines of display data. The traditional approach for this temporary storage element for NxN image filter is either by using N blocks of memory to store N lines of display data with single-port six-transistor (6T) SRAM bit-cells or by using N-1 blocks of memory to store N-1 lines of display data with dual-port eight-transistor (8T) SRAM bit-cells. In this paper, a pseudo multi-port SRAM circuit is proposed for NxN filter in image processing in a display driver integrated circuit (IC). By using pre-read mechanism and word-line/column selection signal forwarding technique, the proposed approach only stores N-1 lines of display data and can use the small single-port 6T SRAM bit-cells. For a 3 x 3 filter application, the proposed approach reduces the overall layout area by 50.3% and 30.2% compared to the traditional dual-port 8T and single-port 6T memory implementations, respectively, in an industrial 0.18-mu m CMOS technology. Furthermore, the power used to perform a 3x3 filter operation is reduced by 47% and 30.8% with the proposed approach as compared to the traditional dual-port 8T and signal-port 6T memory circuits, respectively, with slight degradation of the access speed.