Logic Optimization, Complex Cell Design, and Retiming of Single Flux Quantum Circuits

被引:20
|
作者
Katam, Naveen Kumar [1 ]
Pedram, Massoud [1 ]
机构
[1] Univ Southern Calif, Los Angeles, CA 90007 USA
关键词
Carry look-ahead adders (CLAs); circuit synthesis; fanout; single flux quantum (SFQ) circuits;
D O I
10.1109/TASC.2018.2856833
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Single flux quantum (SFQ) technology has emerged as a promising beyond-CMOS technology with Josephson junctions (JJs) as active devices in a superconducting circuit. In this paper, we (i) describe the algorithms and the methodology we used to synthesize a synchronous SFQ circuit using a CMOS logic synthesis tool by adding new features to the tool and by modifying the existing features; (ii) introduce the concept of two kinds of complex cells: (a) stand-alone cells and (b) interconnected cells along with the advantage gained by these complex cells through the results of synthesized SFQ netlists. Design of stand-alone complex cells presented here includes AND and or gates with more-than-two inputs, high-fanout splitters, and "A+BC" cell. Circuits of decoders, multiplexers, and carrylook-ahead adders are synthesized with complex cells, and the advantage in terms of JJ count and latency is presented. We have also investigated the possibility of SFQ cells supporting multiple fanout drive capability by modifying the input/output interfaces of SFQ standard cells. In this direction, an algorithm to modify the input interface of a cell so that it can be driven along with similar cells by a single splitter output is presented along with the results for a simple clock-distribution line with multiple-fanout capability.
引用
收藏
页数:9
相关论文
共 50 条
  • [41] An Efficient Pipelined Architecture for Superconducting Single Flux Quantum Logic Circuits Utilizing Dual Clocks
    Pasandi, Ghasem
    Pedram, Massoud
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2020, 30 (02)
  • [42] A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits
    Li, Xi
    Shahsavani, Soheil Nazar
    Zhou, Xuan
    Pedram, Massoud
    Beerel, Peter A.
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2021, 26 (06)
  • [43] A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits
    Wang, Ching-Cheng
    Mak, Wai-Kei
    2021 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN (ICCAD), 2021,
  • [44] A Minimum-Skew Clock Tree Synthesis Algorithm for Single Flux Quantum Logic Circuits
    Shahsavani, Soheil Nazar
    Pedram, Massoud
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2019, 29 (08)
  • [45] Conversion of logic gates in netlists for rapid single flux quantum circuits utilizing confluence of pulses
    Kito N.
    Takagi K.
    Takagi N.
    IPSJ Transactions on System LSI Design Methodology, 2019, 12 : 78 - 80
  • [46] Single-flux-quantum logic circuits exploiting collision-based fusion gates
    Asai, T.
    Yamada, K.
    Amemiya, Y.
    PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 2008, 468 (15-20): : 1983 - 1986
  • [47] Splitter Trees in Single Flux Quantum Circuits
    Jabbari, Tahereh
    Krylov, Gleb
    Kawa, Jamil
    Friedman, Eby G.
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2021, 31 (05)
  • [48] Design and demonstration of adiabatic quantum-flux-parametron logic circuits with superconductor magnetic shields
    Inoue, Kenta
    Takeuchi, Naoki
    Narama, Tatsuya
    Yamanashi, Yuki
    Yoshikawa, Nobuyuki
    SUPERCONDUCTOR SCIENCE & TECHNOLOGY, 2015, 28 (04):
  • [49] Power Optimization Design for Probabilistic Logic Circuits
    Xiao, Ran
    Chen, Chunhong
    2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, : 2593 - 2595
  • [50] Design of domino logic circuits by an optimization method
    Seyedi, A. S.
    Rasouli, S. H.
    Amirabadi, A.
    Afzali-Kusha, A.
    Lucas, C.
    Forouzandeh, B.
    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, : 260 - +