Pipelined Scheduler for Unicast and Multicast Traffic in Input-Queued Switches

被引:0
|
作者
Xiao, Jie [1 ]
Yeung, Kwan L. [1 ]
Jamin, Sugih [2 ]
机构
[1] Univ Hong Kong, Dept Elect & Elect Engn, Hong Kong, Hong Kong, Peoples R China
[2] Univ Michigan, Dept Elect Engn & Comp Sci, Ann Arbor, MI 48109 USA
关键词
Input-queued switch; integrated scheduler; pipelined scheduling; single-bit-single-iteration scheduling;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We focus on designing efficient integrated schedulers for handling mixed unicast and multicast traffic. We consider an input-queued switch with a multicast-capable switch fabric. At each input port of the switch, there are N dedicated unicast VOQs and one shared multicast queue (MQ). An existing approach to the design of integrated scheduler (i.e., a sequential scheduler) is to run two component schedulers, one for multicast and one for unicast, sequentially in each time slot. To minimize the head-of-line blocking of multicast traffic, the multicast scheduler always runs first. But sequentially running two schedulers in each time slot is challenging, especially when the slot duration is small. In this paper, we first propose a pipelined integration of the two component schedulers (i.e., a pipelined scheduler), which allows twice the amount of time for each scheduler to execute. We then extend an existing single-bit-single-iteration unicast scheduler to ensure that even in the presence of multicast traffic, unicast traffic will be starvation-free. This is achieved by giving unicast traffic priority over multicast periodically. Finally, we present arguably the first single-bit-single-iteration multicast scheduling algorithm. Extensive simulation results show that our pipelined scheduler is efficient and provides delay-throughput performance comparable to the sequential scheduler.
引用
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页数:6
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