Parallel graph traversal for FPGA

被引：4

作者：

Ni, Shice ^{[1
]}

Dou, Yong ^{[1
]}

Zou, Dan ^{[1
]}

Li, Rongchun ^{[1
]}

Wang, Qiang ^{[1
]}

机构：

[1] Natl Univ Def Technol, Natl Lab Parallel & Distributed Proc, Changsha, Hunan, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2014年 / 11卷 / 07期

基金：

美国国家科学基金会;

关键词：

FPGA; multi-channel memory; parallel graph traversal;

D O I：

10.1587/elex.11.20130987

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a multi-channel memory based architecture for parallel processing of large-scale graph traversal for field-programmable gate array (FPGA). By designing a multi-channel memory subsystem with two DRAM modules and two SRAM chips and developing an optimized pipelining structure for the processing elements, we achieve superior performance to that of a state-of-the-art highly optimized BFS implementations using the same type of FPGA.

引用

页数：6

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