A toggle MRAM bit modeled in Verilog-A

被引：1
|
作者：
Engelbrecht, Linda M. [1 ]
Jander, Albrecht
Dhagat, Pallavi
Hall, Michael [2 ]
机构：
[1] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA
[2] Washington Univ, St Louis, MO USA
来源：
SOLID-STATE ELECTRONICS | 2010年 / 54卷 / 10期
关键词：
Spintronics; Toggle MRAM; Spinflop; Torque; RANDOM-ACCESS MEMORY;
D O I：
10.1016/j.sse.2010.05.038
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A physically-based behavioral model for a toggle mode magnetic random access memory (MRAM) cell, developed in Verilog-A is presented. The model describes the magnetic behavior of two single-domain, magnetic free-layers coupled through exchange and magnetostatic interactions. The model also includes spin-dynamic effects. The external interface to the model is electrical in nature, consisting of input currents on the word and bit lines and an output in the form of a magnetoresistance based on the orientation of one of the free layers. The model faithfully reproduces toggling of the magnetic state (reversal of magnetization directions of the two layers through an intermediate spin flop state) in response to a conventional box field stimulus. The model will facilitate the design and analysis of complex spintronic or hybrid spintronic-electronic circuits in a simulation environment that is familiar to most circuit designers. (C) 2010 Elsevier Ltd. All rights reserved.
引用
收藏
页码：1135 / 1142
页数：8
相关论文
共 50 条
  • [1] Analog design with Verilog-A
    Miller, I
    FitzPatrick, D
    Aisola, R
    1997 IEEE INTERNATIONAL VERILOG HDL CONFERENCE, PROCEEDINGS, 1997, : 64 - 68
  • [2] A 4-mb toggle MRAM based on a novel bit and switching method
    Engel, BN
    Akerman, J
    Butcher, B
    Dave, RW
    DeHerrera, M
    Durlam, M
    Grynkewich, G
    Janesky, J
    Pietambaram, SV
    Rizzo, ND
    Slaughter, JM
    Smith, K
    Sun, JJ
    Tehrani, S
    IEEE TRANSACTIONS ON MAGNETICS, 2005, 41 (01) : 132 - 136
  • [3] On code coverage measurement for Verilog-A
    Sha, YB
    Lee, MS
    Liu, CNJ
    NINTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS, 2004, : 115 - 120
  • [4] Study of Memristor with Verilog-A Model
    Baghel, Vijay Singh
    Akashe, Shyam
    JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2016, 11 (2-3): : 89 - 97
  • [5] Modeling of Silicon Photonics Devices with Verilog-A
    Martin, P.
    Gays, F.
    Grellier, E.
    Myko, A.
    Menezo, S.
    2014 29TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS PROCEEDINGS - MIEL 2014, 2014, : 209 - 212
  • [6] Best Practices for Compact Modeling in Verilog-A
    McAndrew, Colin C.
    Coram, Geoffrey J.
    Gullapalli, Kiran K.
    Jones, J. Robert
    Nagel, Laurence W.
    Roy, Ananda S.
    Roychowdhury, Jaijeet
    Scholten, Andries J.
    Smit, Geert D. J.
    Wang, Xufeng
    Yoshitomi, Sadayuki
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2015, 3 (05): : 383 - 396
  • [7] Advanced circuit and device modelin with Verilog-A
    Mijalkovic, Slobodan
    2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, 2006, : 471 - 474
  • [8] Circuit reliability simulation based on Verilog-A
    Kole, Marq
    BMAS 2007: PROCEEDINGS OF THE 2007 IEEE INTERNATIONAL BEHAVIORAL MODELING AND SIMULATION WORKSHOP, 2007, : 58 - 63
  • [9] Compact Model of a CBRAM Cell in Verilog-A
    Reyboz, M.
    Onkaraiah, S.
    Palma, G.
    Vianello, E.
    Perniola, L.
    2012 12TH ANNUAL NON-VOLATILE MEMORY TECHNOLOGY SYMPOSIUM, 2012, : 94 - 97
  • [10] Suppressing derivatives of selected variables in Verilog-A
    Huszka, Zoltan
    Molnar, Kund
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2019, 47 (05) : 805 - 811
12345