Transitioning Spiking Neural Network Simulators to Heterogeneous Hardware

被引:3
|
作者
Quang Anh Pham Nguyen [1 ,2 ]
Andelfinger, Philipp [1 ,2 ]
Tan, Wen Jun [1 ,2 ]
Cai, Wentong [2 ]
Knoll, Alois [2 ,3 ,4 ]
机构
[1] TUM Create Ltd, 1 Create Way 10-02 CREATE Tower, Singapore 138602, Singapore
[2] Nanyang Technol Univ, 50 Nanyang Ave, Singapore 639798, Singapore
[3] Tech Univ Munich, Munich, Germany
[4] Univ Munich, Arcisstr 21, D-80333 Munich, Germany
基金
新加坡国家研究基金会;
关键词
Spiking neural network simulators; types of simulation: parallel & heterogeneous; automatic code transformation; DOMAIN-SPECIFIC LANGUAGE; NEURONS; BRAIN;
D O I
10.1145/3422389
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Spiking neural networks (SNN) are among the most computationally intensive types of simulation models, with node counts on the order of up to 10(11). Currently, there is intensive research into hardware platforms suitable to support large-scale SNN simulations, whereas several of the most widely used simulators still rely purely on the execution on CPUs. Enabling the execution of these established simulators on heterogeneous hardware allows new studies to exploit the many-core hardware prevalent in modern supercomputing environments, while still being able to reproduce and compare with results from a vast body of existing literature. In this article, we propose a transition approach for CPU-based SNN simulators to enable the execution on heterogeneous hardware (e.g., CPUs, GPUs, and FPGAs), with only limited modifications to an existing simulator code base and without changes to model code. Our approach relies on manual porting of a small number of core simulator functionalities as found in common SNN simulators, whereas the unmodified model code is analyzed and transformed automatically. We apply our approach to the well-known simulator NEST and make a version executable on heterogeneous hardware available to the community. Our measurements show that at full utilization, a single GPU achieves the performance of about 9 CPU cores. A CPU-GPU co-execution with load balancing is also demonstrated, which shows better performance compared to CPU-only or GPU-only execution. Finally, an analytical performance model is proposed to heuristically determine the optimal parameters to execute the heterogeneous NEST.
引用
收藏
页数:26
相关论文
共 50 条
  • [31] Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations
    Carrillo, Snaider
    Harkin, Jim
    McDaid, Liam J.
    Morgan, Fearghal
    Pande, Sandeep
    Cawley, Seamus
    McGinley, Brian
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2013, 24 (12) : 2451 - 2461
  • [32] Spatiotemporal contextual learning network with excitatory and inhibitory synapses for spiking neural network hardware
    Orima, Takemori
    Horio, Yoshihiko
    Tsuji, Takeru
    IEICE NONLINEAR THEORY AND ITS APPLICATIONS, 2024, 15 (04): : 796 - 810
  • [33] An ultrafast neural network-based hardware acceleration for nonlinear systems' simulators
    Awaad, Tasneem A.
    Elbehery, Abdelrahman M.
    Abdelhamid, Amany
    Elsokkary, Salma K.
    Ali, Youssef M.
    Salah, Khaled
    Salam, Mohamed Abdel
    El-Kharashi, M. Watheq
    COMPUTERS & ELECTRICAL ENGINEERING, 2019, 79
  • [34] A flexible graphical user interface for embedding heterogeneous neural network simulators
    Drossu, R
    Obradovic, Z
    Fletcher, J
    IEEE TRANSACTIONS ON EDUCATION, 1996, 39 (03) : 367 - 374
  • [35] A Scatter-and-Gather Spiking Convolutional Neural Network on a Reconfigurable Neuromorphic Hardware
    Zou, Chenglong
    Cui, Xiaoxin
    Kuang, Yisong
    Liu, Kefei
    Wang, Yuan
    Wang, Xinan
    Huang, Ru
    FRONTIERS IN NEUROSCIENCE, 2021, 15
  • [36] Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations
    Carrillo, Snaider
    Harkin, Jim
    McDaid, Liam
    Pande, Sandeep
    Cawley, Seamus
    Morgan, Fearghal
    ARTIFICIAL NEURAL NETWORKS AND MACHINE LEARNING - ICANN 2011, PT I, 2011, 6791 : 77 - +
  • [37] Optimal Mapping of Spiking Neural Network to Neuromorphic Hardware for Edge-AI
    Xiao, Chao
    Chen, Jihua
    Wang, Lei
    SENSORS, 2022, 22 (19)
  • [38] Error estimation and correction in a spiking neural network for map formation in neuromorphic hardware
    Kreiser, Raphaela
    Waibel, Gabriel
    Armengol, Nuria
    Renner, Alpha
    Sandamirskaya, Yulia
    2020 IEEE INTERNATIONAL CONFERENCE ON ROBOTICS AND AUTOMATION (ICRA), 2020, : 6134 - 6140
  • [39] CuSNP: Spiking Neural P Systems Simulators in CUDA
    Carandang, Jym Paul A.
    Villaflores, John Matthew B.
    Cabarle, Francis George C.
    Adorna, Henry N.
    Martinez-del-Amor, Miguel A.
    ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, 2017, 20 (01):
  • [40] Fixed latency on-chip interconnect for hardware spiking neural network architectures
    Pande, Sandeep
    Morgan, Fearghal
    Smit, Gerard
    Bruintjes, Tom
    Rutgers, Jochem
    McGinley, Brian
    Cawley, Seamus
    Harkin, Jim
    McDaid, Liam
    PARALLEL COMPUTING, 2013, 39 (09) : 357 - 371