On-chip iDD pulse response method using a high-speed dynamic current sensor

被引:0
|
作者
Aceved, GOD [1 ]
Ramírez-Angulo, J [1 ]
机构
[1] New Mexico State Univ, Klipsch Sch Elect & Comp Engn, Las Cruces, NM 88003 USA
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This paper presents design considerations for a high-speed dynamic current sensor for iDD analysis. This testing scheme, known as the iDD pulse response method is a built-in scheme for analog, digital and mixed-signal circuitry compatible with the IEEE 1149.4 mixed-signal test bus standard. A high-speed dynamic current sensor is required for this method-and is described in this paper. Simulation results are provided for the current sensor used to observe the iDD supply current of analog and digital devices. Simulation results include iDD waveforms of defect-free circuits, for circuits with parametric/global faults, and circuits with catastrophic faults. This testing technique serves as an early screening method for defect-free circuits and will potentially allow a fault-free IC to enter the market in significantly less time.
引用
收藏
页码:282 / 285
页数:4
相关论文
共 50 条
  • [31] Performance limitation of on-chip global interconnects for high-speed signaling
    Tsuchiya, A
    Gotoh, Y
    Hashimoto, M
    Onodera, H
    PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2004, : 489 - 492
  • [32] Behavioral Model for High-Speed SAR ADCs With On-Chip References
    Dominguez-Matas, Carlos
    Gines, Antonio
    Otin, Aranzazu
    Gutierrez, Valentin
    Leger, Gildas
    Peralias, Eduardo
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 31 (12) : 1918 - 1930
  • [33] On-chip graphene optoelectronic devices for high-speed modulation and photodetection
    Shiue, Ren-Jye
    Gan, Xuetao
    Englund, Dirk
    PHOTONIC AND PHONONIC PROPERTIES OF ENGINEERED NANOSTRUCTURES IV, 2014, 8994
  • [34] High-Speed and On-Chip Optical Switch Based on a Graphene Microheater
    Nakamura, Shoma
    Sekiya, Kota
    Matano, Shinichiro
    Shimura, Yui
    Nakade, Yuuki
    Nakagawa, Kenta
    Monnai, Yasuaki
    Maki, Hideyuki
    ACS NANO, 2022, 16 (02) : 2690 - 2698
  • [35] Novel on-chip circuit for jitter testing in high-speed PLLs
    Cazeaux, JM
    Omaña, M
    Metra, C
    IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2005, 54 (05) : 1779 - 1788
  • [36] REGISTERED BIPOLAR PROMS TARGET ON-CHIP DIAGNOSTICS AT HIGH-SPEED
    LEONARD, M
    ELECTRONIC PRODUCTS MAGAZINE, 1986, 28 (16): : 24 - +
  • [37] Performance limitation of on-chip global interconnects for high-speed signaling
    Tsuchiya, A
    Hashimoto, M
    Onodera, H
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2005, E88A (04) : 885 - 891
  • [38] Inductance model and analysis methodology for high-speed on-chip interconnect
    Gala, K
    Blaauw, D
    Zolotov, V
    Vaidya, PM
    Joshi, A
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (06) : 730 - 745
  • [39] Design guideline for resistive termination of on-chip high-speed interconnects
    Tsuchiya, A
    Hashimoto, M
    Onodera, H
    CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2005, : 613 - 616
  • [40] Frequency distribution modeling for high-speed microprocessors using on-chip ring-oscillators
    Carulli, JM
    Wrobbel, DC
    Mehta, A
    Krause, KE
    Campbell, BE
    Valente, FA
    IN-LINE METHODS AND MONITORS FOR PROCESS AND YIELD IMPROVEMENT, 1999, 3884 : 146 - 155