Design guideline for resistive termination of on-chip high-speed interconnects

被引：0
|
作者：
Tsuchiya, A [1 ]
Hashimoto, M [1 ]
Onodera, H [1 ]
机构：
[1] Kyoto Univ, Kyoto 6068501, Japan
来源：
CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2005年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper discusses the resistive termination of on-chip high-performance interconnects. Resistive termination can improve the bandwidth of on-chip interconnects, on the other hands, increases the power dissipation. Therefore a design guideline for resistive termination is necessary. In this paper, we propose a method to determine the termination of on-chip interconnects. The termination derived by the proposed method provides minimum sensitivity to process variation as well as maximum eye-opening in voltage.
引用
收藏
页码：613 / 616
页数：4
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