A Design of 12-Bit Low-Power Pipelined ADC Using TIQ Technique

被引：0

作者：

Vinay, B. K. ^{[1
]}

Mala, S. Pushpa ^{[2
]}

Deekshitha, S. ^{[1
]}

Sunil, M. P. ^{[3
]}

机构：

[1] CMRIT, Dept Elect & Commun, Bengaluru, India

[2] Dayananda Sagar Univ, Dept Elect & Commun, Bengaluru, India

[3] Jain Univ, Sch Engn & Technol, Dept Elect & Commun, Bengaluru, India

来源：

INTELLIGENT COMPUTING AND COMMUNICATION, ICICC 2019 | 2020年 / 1034卷

关键词：

Residue voltage; Threshold inverter quantizer; Differential amplifier; Flash ADC; Pipelined stage;

D O I：

10.1007/978-981-15-1084-7_58

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A CMOS 12-bit pipeline analog to digital converter (ADC) is designed for improved speed, resolution and low power consumption. The design incorporates 12 stages of 1-bit ADC cascaded to form pipelined architecture, with each stage containing a sub-ADC with a new approach of threshold inverter quantizer (TIQ) which substitutes the resistor array implementation and amultiplying digital to analog converter (MDAC) for quantized approximation of input voltage. The residue voltage is amplified in gain stage by closed-loop differential amplifier to have appropriate quantized output at the next stage. The sampling frequency is 200 MHz in 180 nm technology, and speed is 100 MSps and power is 50 mW, 0.5 pJ/step with 12-bit resolution.

引用

页码：601 / 611

页数：11

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