Implementation of a Reconfigurable Neural Network in FPGA

This article proposes a new hardware implementation for a Reconfigurable Neural Network for systems in which the topology needs flexibility. The used architecture is a Multi-Layer Perceptron, where the entry of a layer depends on the output of the previous layer. The approach allows flexibility in the number of network inputs, neurons, layers and in the activation function executed by neurons. Despite having been developed for FPGAs, the implemented circuit allows its implementation in ASIC, since it does not use proprietary internal blocks of the FPGA. By submitting the network to approximation tests, its operation and flexibility has been checked and validated.