Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness

被引：3

作者：

Wang, Yuan ^{[1
]}

Lu, Guangyi ^{[1
]}

Wang, Yize ^{[1
]}

Zhang, Xing ^{[1
]}

机构：

[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2017年 / E100C卷 / 03期

关键词：

electrostatic discharge (ESD); robustness; false-triggering immunity; transmission-line-pulsing (TLP) test; NANOSCALE CMOS TECHNOLOGY; PROTECTION; DESIGN; NMOS;

D O I：

10.1587/transele.E100.C.344

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work reports a novel power-rail electrostatic discharge (ESD) clamp circuit with parasitic bipolar-junction-transistor (BJT) and channel parallel shunt paths. The parallel shunt paths are formed by delivering a tiny ratio of drain voltage to the gate terminal of the clamp device in ESD events. Under such a mechanism, the proposed circuit achieves enhanced robustness over those of both gate-grounded NMOS (ggNMOS) and the referenced gate-coupled NMOS (gcNMOS). Besides, the proposed circuit also achieves improved fast power-up immunity over that of the referenced gcNMOS. All investigated designs are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and human-body-model (HBM) test results have both confirmed the performance enhancements of the proposed circuit. Finally, the validity of the achieved performance enhancements on other trigger circuits is essentially revealed in this work.

引用

页码：344 / 347

页数：4

共 45 条

[41] The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
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[42] New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
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[43] Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process基于65纳米CMOS工艺的静态触发型电源钳位ESD保护电路设计
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[44] Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
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[45] Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
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