A Low Phase-noise Low-power PLL in 0.13-μm CMOS for Low Voltage Application

被引：0

作者：

Guo, Q. ^{[1
]}

Zhou, H. F. ^{[1
]}

Cheng, W. W. ^{[1
]}

Han, Y. ^{[1
]}

Han, X. X. ^{[1
]}

Liang, X. ^{[1
]}

机构：

[1] Zhejiang Univ, Dept Informat Sci & Elect Engn, Hangzhou 310027, Zhejiang, Peoples R China

来源：

PIERS 2009 MOSCOW VOLS I AND II, PROCEEDINGS | 2009年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low voltage, low power phase-locked loop (PLL) using a standard 0.13-mu m CMOS 1P8M process is presented. The voltage-controlled oscillator (VCO) can operate from a 0.5 V supply while the phase-frequency detector (PFD), charge pump (CP) and the divider use 0.8 V supply. The dc power consumption of the PLL is only 2.5 mW. Due to the use of the wideband nulling of flicker noise up conversion technique, the worst phase noise of the whole tuning range is 122.5 dBc/Hz at 1 MHz frequency offset and the phase noise displays little dependence on the frequency tuning.

引用

页码：1540 / 1544

页数：5

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