共 50 条
- [32] Modular System-Level Architecture for Concurrent Cell Balancing [J]. 2013 50TH ACM / EDAC / IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2013,
- [33] System-level simulation environment for system-on-chip design [J]. Proc Annu IEEE Int ASIC Conf Exhib, (58-62):
- [34] A system-level simulation environment for system-on-chip design [J]. 13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2000, : 58 - 62
- [35] CONCURRENT DESIGN AND ANALYSIS OF THE NAVIGATOR WEARABLE COMPUTER-SYSTEM - THE THERMAL PERSPECTIVE [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART A, 1995, 18 (03): : 567 - 577
- [36] System-level assertions: approach for electronic system-level verification [J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2015, 9 (03): : 142 - 152
- [38] System-Level Design Trade-offs for Truly Wearable Wireless Medical Devices [J]. 2010 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC), 2010, : 1441 - 1444
- [39] System-Level Power Management for Low-Power SOC Design [J]. 2011 TENTH INTERNATIONAL SYMPOSIUM ON DISTRIBUTED COMPUTING AND APPLICATIONS TO BUSINESS, ENGINEERING AND SCIENCE (DCABES), 2011, : 412 - 416
- [40] LTE-A system downlink HARQ system-level design and simulation [J]. APPLIED SCIENCE, MATERIALS SCIENCE AND INFORMATION TECHNOLOGIES IN INDUSTRY, 2014, 513-517 : 2518 - 2521