Performance analysis of a-Si:H detectors deposited on CMOS chips

Image and particle sensors based on thin-film on CMOS technology are currently being developed at our laboratory. In this technology, amorphous silicon detectors are vertically integrated on top of dedicated CMOS chips. For both, vision and particle detection, this approach is expected to enhance the performances. In fact very high fill factors, increased sensitivity, and integration level, coupled with extremely low dark current density values can potentially be attained. A first optimization of the a-Si:H diodes (>1mm(2)) on glass substrates, with the primary focus on reducing dark current densities, gave J(dark) values as low as 1 pA/cm(2) (at -1 V for 1 mum thick detectors). These detectors were then deposited on CMOS readout chips, but so far this step was unfortunately accompanied by an increase in J(dark) to values over 10 nA/cm(2). Here, the possible cause for such an increase in J(dark) as well as possible "remedies" against this effect will be discussed; the principle cause is supposed to be the influence of chip topology. Possible solutions include surface treatments as well as the use of metal-i-p diode configuration. Results obtained so far with these methods are given.