Reducing Reconfiguration Time in FPGAs

Despite the growing popularity of field-programmable gate arrays (FPGA), this technology still suffers from drawbacks such as larger area, higher power consumption and longer runtime than application-specific integrated circuits (ASIC). Reconfiguration capability gives FPGAs an advantage over ASIC and can make it a more appropriate option for implementing some applications. One important issue regarding the reconfiguration process is the time it takes to carry out this procedure. This paper seeks to accelerate the reconfiguration process by using a bitstream compression method with a primary focus on FPGA architecture. Since multiplexers are among the main components of FPGAs, the proposed method is focused on encoding and compression of configuration bitstream for such resources. In addition, the bitstream format and the decompression operation are designed to obtain desirable results in terms of area overhead and time improvement. Results of experiments show that in comparison to the basic scheme, the proposed design improves the reconfiguration time by 33%.