An evolutionary technique for reducing the duration of Reconfigurable Scan Network test

The growing need for effectively accessing registers (called instruments) related to non-functional purposes (e.g., test, debug, calibration) in many electronic devices pushed towards the development of new solutions, including the IEEE 1687 standard. The approach supported by these solutions allows a flexible access to embedded instruments through the Boundary Scan interface via a set of reconfigurable scan chains composing a Reconfigurable Scan Network (RSN). Since permanent faults may affect the circuitry implementing them, several works recently proposed techniques to automatically generate a suitable sequence of input stimuli able to detect them. The common approach is based on forcing the IEEE 1687 network to undergo a sequence of test sessions, each composed of a configuration phase and a test phase. By properly selecting the sequence of network configurations to be used, we can guarantee that the method can test any permanent fault possibly affecting the network. Clearly, the cost of this test directly depends on its duration. This paper faces the issue of generating a test sequence for a generic RSN possibly reducing its duration and proposes a method based on an evolutionary algorithm. We provide some experimental results gathered on the standard set of benchmarks RSNs, showing that the approach is able to produce optimized test sequences in 9 cases out of 16. In some cases, the reduction in test time is larger than 20%.