A 600 MSPS 8-bit folding ADC in 0.18μm CMOS

被引：8

作者：

Wang, ZY ^{[1
]}

Pan, H ^{[1
]}

Chang, CM ^{[1
]}

Yu, HR ^{[1
]}

Chang, MF ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90024 USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

A/D converter; distributed track-and-holds; capacitive averaging; folding and interpolation;

D O I：

10.1109/VLSIC.2004.1346638

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An 8-bit folding A/D converter (ADC) achieves signal-to-noise plus distortion ratio (SNDR) of 40 dB at 600 MSample/s (MSPS) for input signals up to 200 MHz in standard 0.18-mum CMOs. Distributed T/Hs at outputs of the first-stage pre-amplifiers are employed instead of a dedicated front-end T/H. Lateral capacitors are inserted between adjacent T/H outputs to average the random mismatches in charge injection and clock skew among the distributed T/Hs. The ADC consumes 0.5-mm(2) effective chip area and dissipates 207mW from a 1.8V supply.

引用

页码：424 / 427

页数：4

共 50 条

[31] An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC
Sarkar, Santanu
Banerjee, Swapna
2009 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2009, : 268 - 273
[32] A 500MSPS 8-bit ADC card based on time-interleaving technique
Hao, Zhou
Qi, An
ICEMI 2007: PROCEEDINGS OF 2007 8TH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOL IV, 2007, : 582 - 586
[33] Low Power 8-bit 200MSPS Time-Interleaved Pipelined ADC
Song Jinghui
Wang Zongmin
Zhang Zhuo
Zhou Liang
WORLD CONGRESS ON ENGINEERING AND COMPUTER SCIENCE, WCECS 2011, VOL II, 2011, : 766 - 771
[34] Accuracy of discrete-time signal reconstruction registered at 8-bit high-rate ADC output based on 0.18μm CMOS technology
Porshnev, S. V.
Kusaykin, D. V.
2015 INTERNATIONAL SIBERIAN CONFERENCE ON CONTROL AND COMMUNICATIONS (SIBCON), 2015,
[35] A 25Msps 8-bit/10Msps 10-bit CMOS data acquisition IC for digital storage oscilloscopes
Kusayanagi, N
Choi, T
Hiwatashi, M
Segami, M
Akasaka, Y
Wakabayashi, T
PROCEEDINGS OF THE IEEE 1997 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1997, : 301 - 304
[36] A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS
Zhou, Xiong
Li, Qiang
2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2012,
[37] An 8-bit 200 ms/s CMOS folding/interpolating ADC with a reduced number of preamplifiers using an averaging technique
Heo, SC
Jang, YC
Park, SH
Park, HJ
15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2002, : 80 - 83
[38] A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS
Niket Agrawal
Roy Paily
Analog Integrated Circuits and Signal Processing, 2010, 63 : 273 - 281
[39] A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS
Agrawal, Niket
Paily, Roy
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2010, 63 (02) : 273 - 281
[40] 低功耗8-bit 200MSPS时间交织流水线ADC
张倬
王宗民
周亮
冯文晓
电子产品世界, 2013, 20 (12) : 71 - 73

← 1 2 3 4 5 →