A 600 MSPS 8-bit folding ADC in 0.18μm CMOS

被引：8

作者：

Wang, ZY ^{[1
]}

Pan, H ^{[1
]}

Chang, CM ^{[1
]}

Yu, HR ^{[1
]}

Chang, MF ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90024 USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

A/D converter; distributed track-and-holds; capacitive averaging; folding and interpolation;

D O I：

10.1109/VLSIC.2004.1346638

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An 8-bit folding A/D converter (ADC) achieves signal-to-noise plus distortion ratio (SNDR) of 40 dB at 600 MSample/s (MSPS) for input signals up to 200 MHz in standard 0.18-mum CMOs. Distributed T/Hs at outputs of the first-stage pre-amplifiers are employed instead of a dedicated front-end T/H. Lateral capacitors are inserted between adjacent T/H outputs to average the random mismatches in charge injection and clock skew among the distributed T/Hs. The ADC consumes 0.5-mm(2) effective chip area and dissipates 207mW from a 1.8V supply.

引用

页码：424 / 427

页数：4

共 50 条

[1] An 8-bit, 200 MSPS folding and interpolating ADC
Moldsvor, O
Ostrem, GS
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1998, 15 (01) : 37 - 47
[2] An 8-bit, 200 MSPS Folding and Interpolating ADC
Øystein Moldsvor
Geir S. Østrem
Analog Integrated Circuits and Signal Processing, 1998, 15 : 37 - 47
[3] A 8-bit 2Gs/s flash ADC in 0.18μm CMOS
Li, Qizhang
Li, Zheying
2012 INTERNATIONAL WORKSHOP ON INFORMATION AND ELECTRONICS ENGINEERING, 2012, 29 : 693 - 698
[4] An 8-bit, 20 MSPS pipelined ADC
Wagdy, MF
Liu, ZL
Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3, 2003, : 168 - 173
[5] MDAC Design for an 8-bit 40 MS/s Pipelined ADC in a 0.18μm CMOS Process
Dendouga, Abdelghani
Oussalah, Slimane
Lakhdar, Nacereddine
Lakehal, Brahim
2018 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND ELECTRICAL ENGINEERING (ICCEE), 2018, : 160 - 162
[6] A 600-MSPS 8-bit CMOS ADC Using Distributed Track-and-Hold With Complementary Resistor/Capacitor Averaging
Wang, Zhengyu
Chang, Mau-Chung Frank
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2008, 55 (11) : 3621 - 3627
[7] A 160MSPS 8-bit pipeline based ADC
Halder, S
Ghosh, A
Prasad, RS
Chatterjeee, A
Banerjee, S
18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS, 2005, : 313 - 318
[8] An 8-bit 10 kS/s 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities
Marjonen, J.
Pesonen, N.
Vermesan, O.
Aberg, M.
Oja, A.
Rustad, H.
Rusu, C.
Enoksson, P.
2007 NORCHIP, 2007, : 100 - +
[9] An 8-bit 300MS/s switched-current pipeline ADC in 0.18 μm CMOS
Sedighi, Behnam
Bakhtiar, Mehrdad Sharif
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 1481 - 1484
[10] An 8-bit 250MSPS CMOS pipelined ADC using open-loop architecture
Koo, JH
Kim, YJ
Kim, SH
Yun, WJ
Lim, SI
Kim, S
PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 94 - 97

← 1 2 3 4 5 →