Optimization and realization of sub 100nm channel length Lateral Asymmetric Channel P-MOSFETS

被引：0

作者：

Hemkar, M ^{[1
]}

Vasi, J ^{[1
]}

Rao, VR ^{[1
]}

Cheng, B ^{[1
]}

Woo, JCS ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India

来源：

PROCEEDING OF THE TENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOLS I AND II | 2000年 / 3975卷

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Lateral Asymmetric Channel (LAC) p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated and characterized as part of this study. We show, for the first time, the results of extensive experiments done on LAC p-MOSFETs, including the effect of tilt angle of V-T adjust implant, on the device performance. Both uniform and asymmetric devices are fabricated on the same wafer for more accurate comparison.

引用

页码：584 / 587

页数：4

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