Substrate and Trench Design for GaN-on-EBUS Power IC Platform

A GaN on engineered bulk silicon (GaN-on- EBUS) power IC platform has been recently proposed and demonstrated. This platform adopts p-n junctions embedded in bulk Si substrate along with surrounding deep trenches to eliminate the crosstalk between the high-side (HS) and low-side (LS) power switches in bridge-type circuits used for power electronics. The p-n junctions could lead to an increase in output capacitances and thereof induce additional COSS losses (Delta EOSS- p-n). Delta EOSS-p-n is attributed to the doping concentration and backside termination scheme. Meanwhile, the trenches ought to be carefully designed to provide a sufficient isolation margin for the high voltage operation of the overlaying GaN HEMTs. This article focuses on the design of the substrate with respect to the doping concentration and the backside termination with the purpose of reducing Delta EOSS-p-n. The trench design is investigated in terms of the trenches' dimensions to maintain a sufficiently high isolation capability. Based on those studies, an EBUS substrate is implemented for the first time by adopting a 4-in high-resistivity floating-zone (FZ) Si wafer with a Schottky contact on the backside. An industrial standard 200-V GaN film is successfully grown on top. The EBUS substrate delivers appreciably decreased Delta EOSS-p-n and offers a breakdown voltage (BV) of over 1690 V.