A direct-conversion RF front-end in a 65-nm CMOS

被引：1
|
作者：
Kaukovuori, J. [1 ]
Ryynanen, J. [1 ]
Halonen, K. A. I. [1 ]
机构：
[1] Aalto Univ, Elect Circuit Design Lab, POB 3000, FIN-02015 Helsinki, Finland
来源：
24TH NORCHIP CONFERENCE, PROCEEDINGS | 2006年
关键词：
D O I：
10.1109/NORCHP.2006.329218
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 2.4-GHz direct-conversion RF front-end designed in a 65-nm CMOS process is described in this paper. The front-end includes an LNA, folded quadrature mixers, a local oscillator (LO) divider, and LO buffers. The front-end consumes 29.3 mA from a 1.2-V power supply and according to simulations it achieves 39-dB voltage gain, 1.5-dB minimum spot noise figure, and -17-dBm IIP3.
引用
收藏
页码：235 / +
页数：2
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