Full three-dimensional analysis of a non-volatile memory cell

We demonstrate the applicability of three-dimensional process simulation and show its benefit for the development of modem semiconductor technology. Therefore we have performed a process simulation for a Caywood-EEPROM memory cell, followed by the extraction of the coupling capacitance. Such a kind of analysis allows to optimize the layout of the EEPROM memory cell as well as the process parameters. Additionally we show that it is sufficient for the simulation of various process steps to apply simplified empirical models without loosing accuracy in the extracted parameters since the physical behavior of deposition and etching processes is often empirically well characterized within a certain process window.