Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network

Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes tor most modern wireless communication systems include multiple code rates, various block lengths. and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any Input number (IN) and shift number (SN) for cyclic shift In this paper we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network We prove that Banyan network ha, the nonblocking property or cyclic shift when the IN is power of 2, and give the control signal generating algorithm Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN In addition, we present the hardware design of the control signal generator. which can greatly reduce the hardware complexity and latency The synthesis results using the TSMC 0 mu m pin library demonstrate that the proposed permutation network can be implemented with the area of 0 546 mm(2) and the frequency of 292 MHz