A New Linear Readout Circuit for a CMOS Image Sensor

被引：1

作者：

Teymouri, M. ^{[1
]}

Hadidi, Kh. ^{[1
]}

Khoei, A. ^{[1
]}

机构：

[1] Urmia Univ, Microelect Res Ctr, Orumiyeh, Iran

来源：

2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2 | 2009年

关键词：

D O I：

10.1109/ECCTD.2009.5274955

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a high linearity, low area and low power column-parallel readout circuit with a modified 3 transistor active pixel sensor (3T-APS). Each column readout circuit consumes 43uW power provided from the 3.3V power supply and a small layout size of 10x300um(2) is integrated in the 512 columns at one side of the pixel array. The modified pixel achieves the signal saturation voltage is the same as the standard APS structure, and the readout circuit linearity range is 99.9%. A high linearity 512x512 pixel CMOS image sensor with the proposed column-parallel readout circuit is designed based on 0.35um 2P4M standard CMOS technology.

引用

页码：213 / 216

页数：4

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