Scan latch design for delay test

被引：16

作者：

Savir, J ^{[1
]}

机构：

[1] New Jersey Inst Technol, ECE Dept, Newark, NJ 07102 USA

来源：

ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY | 1997年

关键词：

LSSD; SRL; BIST; LFSR; MISR; delay test;

D O I：

10.1109/TEST.1997.639650

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting one of the new SRLs are reported on three pilot chips.

引用

页码：446 / 453

页数：8

共 50 条

[11] Enabling LOS Delay Test with Slow Scan Enable
Ahlawat, Satyadev
Vaghani, Darshit
Gulve, Rohini
Singh, Virendra
PROCEEDINGS OF 2016 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS), 2016,
[12] Improving delay test quality for boundary scan circuit
Peng, XG
ICEMI '97 - CONFERENCE PROCEEDINGS: THIRD INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, 1997, : 451 - 454
[13] A BIST structure to test delay faults in a scan environment
Girard, P
Landrault, C
Moreda, V
Pravossoudovitch, S
Virazel, A
SEVENTH ASIAN TEST SYMPOSIUM (ATS'98), PROCEEDINGS, 1998, : 435 - 439
[14] Hybrid delay scan: A low hardware overhead scan-based delay test technique for high fault coverage and compact test sets
Wang, S
Liu, X
Chakradhar, ST
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1296 - 1301
[15] Design for boundary-scan test
Journal of Japan Institute of Electronics Packaging, 2020, 23 (03) : 243 - 247
[16] DELAY-FAULT TEST-GENERATION AND SYNTHESIS FOR TESTABILITY UNDER A STANDARD SCAN DESIGN METHODOLOGY
CHENG, KT
DEVADAS, S
KEUTZER, K
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (08) : 1217 - 1231
[17] A power-delay-product efficient and SEU-tolerant latch design
Liu, Pei
Zhao, Tian
Liang, Feng
Zhao, Jizhong
Jiang, Peilin
IEICE ELECTRONICS EXPRESS, 2017, 14 (23):
[18] Delay Testable Design Using Modified Boundary Scan
Yotsuyanagi, Hiroyuki
Hashizume, Masaki
Journal of Japan Institute of Electronics Packaging, 2021, 24 (07) : 663 - 667
[19] A scan-based delay test method for reduction of overtesting
Liu, Hui
Li, Huawel
Hui, Yu
Li, Xiaowei
DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, 2008, : 521 - 526
[20] Research on robust path delay test for scan architecture circuits
Ma, JL
Peng, XG
ISTM/2001: 4TH INTERNATIONAL SYMPOSIUM ON TEST AND MEASUREMENT, VOLS 1 AND 2, CONFERENCE PROCEEDINGS, 2001, : 555 - 558

← 1 2 3 4 5 →