Glitch power minimization by selective gate freezing

被引：25

作者：

Benini, L

De Micheli, D

Macii, A

Macii, E

Poncino, M

Scarsi, R

机构：

[1] Univ Bologna, Dipartimento Elettron Informat & Sistemist, I-40136 Bologna, Italy

[2] Stanford Univ, Comp Syst Lab, Stanford, CA 94305 USA

[3] Politecn Torino, Dipartimento Automat & Informat, I-10129 Turin, Italy

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2000年 / 8卷 / 03期

关键词：

CMOS digital integrated circuits; design automation; power optimization;

D O I：

10.1109/92.845895

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones (called F-Gates) that can be "frozen" by asserting a control signal. A frozen gate cannot propagate glitches to its output. Algorithms for gate selection and clustering that maximize the percentage of filtered glitches and reduce the overhead for generating the control signals are introduced. A power-efficient CMOS implementation of F-Gates is also described. An important feature of the proposed method is that it can be applied in place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.

引用

页码：287 / 298

页数：12

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