Realizing high-voltage junction isolated LDMOS transistors with variation in lateral doping

被引：41

作者：

Hardikar, S ^{[1
]}

Tadikonda, R ^{[1
]}

Green, DW ^{[1
]}

Vershinin, KV ^{[1
]}

Narayanan, EMS ^{[1
]}

机构：

[1] De Montfort Univ, Emerging Technol Res Ctr, Leicester LE1 9BH, Leics, England

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2004年 / 51卷 / 12期

基金：

英国工程与自然科学研究理事会;

关键词：

high-voltage integrated circuits (HVIC); junction isolation; lateral diffused metal-oxide semiconductor (LDMOS); power ICs; reduced surface field (RESURF); variation in lateral doping (VLD);

D O I：

10.1109/TED.2004.839104

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

High-voltage lateral diffused metal-oxide semiconductor (LDMOS) transistors with a variation in the lateral doping (VLD) of drift regions are demonstrated in junction isolation technology using a fully implanted CDMOS process. The VLD profile is realized by using an analytical approach reported previously. The analytical model is verified through simulations and experiment. Results indicate that higher breakdown voltages can be achieved for a given drift length using a VLD profile in comparison to uniform doping while offering a good tradeoff between breakdown voltage and specific on-resistance.

引用

页码：2223 / 2228

页数：6

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