Correlated Statistical SPICE Models for High-Voltage LDMOS Transistors based on TCAD

The aim of the work is to develop a statistical SPICE model for the design of high-voltage ICs based TCAD simulations by considering process variations. From the in line data analysis (together with initial TCAD simulations), critical process variables, which are responsible for the electrical parameter shift, have been chosen for process and device TCAD simulations. An interface between commercial process simulator [1] and Minimos-NT [2] (a device simulator developed by TUW) was also addressed, and statistical process and device simulations were performed for the high-voltage n- and p-channel LDMOS transistors implemented in a HV-CMOS technology. Finally, a statistical SPICE model implementation was done successfully as a linear combination of related SPICE parameters.