CLOCKED SEMI-FLOATING-GATE PSEUDO DIFFERENTIAL PAIR FOR LOW-VOLTAGE ANALOG DESIGN

被引：0
|
作者：
Berg, Y. [1 ]
Mirmotahari, O. [1 ]
机构：
[1] Univ Oslo, Dept Informat, N-0316 Oslo, Norway
来源：
2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2 | 2009年
关键词：
CIRCUITS;
D O I：
10.1109/ECCTD.2009.5275021
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper we present an ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250mV. Simulated data for 90nm CMOS process with a transistor threshold voltage equal to 250mV is included.
引用
收藏
页码：441 / 444
页数：4
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