A VLSI architecture for arithmetic coding of multilevel images

被引：12

作者：

Boo, M ^{[1
]}

Bruguera, JD ^{[1
]}

Lang, T ^{[1
]}

机构：

[1] Univ Calif Irvine, Dept Elect & Comp Engn, Irvine, CA 92664 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1998年 / 45卷 / 01期

关键词：

arithmetic coding; redundant representation; VLSI architecture;

D O I：

10.1109/82.659470

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We describe a VLSI architecture of an arithmetic coder for a multilevel alphabet (256 symbols) that includes the storing and updating of probabilities, the updating of the interval, and the correction of the codeword, The architecture is based on the utilization of redundant arithmetic, and the development of new schemes for storing and updating the cumulative probabilities and updating the range and left point of the current interval. The proposed implementation is compared with one that does not include these improvements, and is shown to result in a significantly lower complexity and shorter cycle.

引用

页码：163 / 168

页数：6

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